The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structures.
In the past, the semiconductor industry utilized various techniques for controlling metal oxide semiconductor (MOS) power transistors. MOS power transistors typically are large and dissipate a large of amount of power, thus, MOS power transistors generally were formed on a single semiconductor die. Typically, such power transistors were driven by semiconductor devices that were external to the power transistor. The driver transistors typically were smaller MOS transistors connected in a totem pole configuration to provide active pull-up and pull-down of the gate of the power transistor.
One problem with these methods and devices was inaccurate timing predictability. The MOS power transistor typically had a large gate capacitance and also had a large inductance due to the bonding wires connecting the gate to external pins. Because of this capacitance and inductance, it was difficult to quickly turn the power transistor on and to turn the power transistor off. This difficulty in turning the transistor on and off lowered the operating frequencies at which the transistor could be operated and also made it difficult to determine the precise time at which the power transistor would turn-on and would turn-off. Typically, a large gate driver or a higher gate voltage was used in order to turn the power transistor on. This larger gate driver or larger voltage increased the system cost.
Another problem was heat dissipation and power loss. The difficulty in turning the transistors on and off resulted in slow rise and fall times that increased the power dissipation of the transistors.
Additionally, it was difficult to maintain the power transistor in an off state. Because of the parasitic drain-to-gate capacitance, current could flow from the drain to the gate when the transistor was in an off-state. This current flow would charge the gate-to-drain capacitance thereby turning on the power transistor.
Accordingly, it is desirable to have a power transistor that has a short and predictable turn-on and turn-off time, that does not allow parasitic currents to affect the gate voltage, that does not require a higher voltage or large driver transistor, and that has a low system cost.